1. Technical Field
The present invention relates to a memory device capable of high speed data transfer to a peripheral device such as a raster display. Such memories are commonly known as Video Random Access memories (VRAMs).
2. Background Art
VRAMs are commonly used as display memories in display systems. A VRAM is essentially a conventional DRAM with the addition of a second port where memory data can be accessed serially. A conventional VRAM comprises a RAM array, a serial access memory (SAM) array, address/control logic, and transfer gates. The SAM comprises a plurality of conventional cross-coupled-latches, each of which is connected to the bit lines of the RAM through the transfer gates. Preferably the RAM is made up of a plurality of pairs of folded bit lines, as in U.S. Pat. No. Re. 32,708 (assigned to Hitachi). Each transfer gate has a first drain/source electrode connected to one of the input nodes of a SAM latch. Under the control of address/control logic, transfer gates are selected by activating their respective gate electrodes, such that data from selected folded bit line pairs is loaded into respective SAM latches. The RAM array is connected to the primary (RAM) port of the VRAM and behaves in a manner identical to that of a DRAM. The SAM array, sometimes called the Shift Register, is connected to the secondary (SAM or Serial) port of the VRAM and may be accessed serially under the control of an external asynchronous clock, the Serial Clock. An address counter generates an address in the SAM, such that data is accessed starting at an addressed SAM latch. The counter is then incremented under the control of the serial clock, so that data from SAM latches having logically adjacent addresses is presented at the serial port.
The address/control logic supervises the address multiplexing on the RAM port and provides all the control and global timing functions of the VRAM. The transfer gates allow data to pass between the RAM array and the SAM array, under the control of the address/control logic.
In modern all-points-addressable display systems, an image to be viewed is stored point-by-point as picture element or pixel data in a display memory. VRAMs are used in such display systems because their two ports can be operated independently and asynchronously, except when data must be transferred between the RAM and SAM arrays. The SAM array usually has the memory capacity of one row (i.e. all of the bit line pairs) of the RAM array, and a full row of memory data is transferred between RAM and SAM in a single data transfer access. The RAM portion of the VRAM is used as the display memory to store pixel data to be displayed and the RAM port is used to update this data. The SAM port provides the pixel data to video generation circuitry which enables it to be passed to and displayed on a raster display device such as a cathode ray tube.
The RAM port is generally operated at the frequency of the update hardware which may be, for example, a graphics processor. The SAM port is generally operated at a frequency dictated by the requirements of the display device. Because the data to be rastered onto the display device is obtained from the SAM port, almost all the RAM port bandwidth is available for update of the pixel data in the display memory.
In some VRAMs the SAM array is divided into two parts, where one part can be loaded from one half of a row in the RAM array and the other part can be loaded from the other half of that row or another row. These types of VRAMs are called Split Shift Register VRAMs. Examples of such split shift register VRAMs are described in U.S. Pat. Nos. 4,855,959 and 4,825,411. Transfer cycles to the two parts can be made independently so that one may be loaded while the other is being used to provide serial data at the serial output port. An output status or QSF pin is usually provided to indicate which half of the SAM is being scanned out.
A common requirement for a display system for multimedia applications is to be able to support more than one display "layer" simultaneously. The number of display layers is often two, although it can be greater than two. One display layer typically contains "natural image" data, for example live television, and the other display layer typically contains an overlay of text or graphics. The image layer can be made visible through the overlay layer with various forms of mixing. For each pixel the overlay is examined to determine if it is "transparent" allowing the corresponding image pixel to be displayed, or whether it is opaque and so must itself be displayed. As this test is performed for every pixel individually it is generally necessary to fetch both overlay and image data for every pixel i.e. fetch two pictures simultaneously and switch between the pictures as determined for each pixel.
A problem which arises in the application of VRAM technology to display systems for multimedia applications is that of how to hold more than one display layer in the display memory and display each layer simultaneously on a display device.
One way of doing this would be to hold each layer in a separate VRAM device and use the VRAM serial port of each device to access the layers simultaneously. However, for low resolution screens one large VRAM, e.g. 4 Mbit, would have enough capacity to hold the pixel data for all the display layers. The use of multiple VRAMs would therefore increase the memory cost by a factor of the number of layers. So, it would be advantageous if all the data streams could be fetched from a single VRAM device.
With conventional VRAM designs this cannot be efficiently achieved for the following reasons. In order to obtain data for, for example, two layers held in two buffers in separate areas of a conventional VRAM it is necessary to first use a data transfer cycle to load the SAM for the first layer, then read some data for the first layer from the serial output port. Then a data transfer cycle must be used to load the SAM for the second layer and data for the second layer is read from the serial output port. This sequence must then be repeated.
Each data transfer cycle takes a considerable time compared to the rate at which the pixel data needs to be supplied at the output port and also requires accesses at the RAM port, thus reducing the bandwidth available to update the RAM contents. To minimize the time lost, two large buffers, one for each display layer, must be used so that many serial data words can be read for each data transfer cycle. Data for the two layers can then be taken from the two buffers simultaneously in order to be displayed. These large buffers and the control logic required add to the size and complexity of the display system.
In the split shift register VRAM described in U.S. Pat. No. 5,063,368, entitled "Video RAM Double Buffer Select Control," assigned to IBM, two frame buffers are stored, one in each half of the rows in a single VRAM. One frame buffer is scanned out to the screen while the other is being updated by the graphics or image processor. A select control signal controls which half of the serial access memory presents data to the output port for each serial clock signal. The SAM pointers for both halves are incremented simultaneously, so that when access is switched between SAM halves respective latches having different (n, n+1) addresses are accessed.